1. Field of the Invention
The present invention relates generally to semiconductor testing and, more particularly, to wafer-level burn-in and testing of components on semiconductor wafers.
2. State of the Art
It is advantageous in semiconductor processing to detect and screen out defective integrated circuits (ICs) as early as possible in the manufacturing process. It is appreciated that many manufactured ICs fail within the first few months or weeks of use due to processing defects. Such a defect profile is commonly known as “infant mortality” and is clearly very undesirable and unacceptable for a typical IC customer. To discover those circuits that are susceptible to infant mortality, manufacturing processes have included high temperature testing of ICs for extended periods of time before shipping products to a customer.
In a typical semiconductor manufacturing process, a multiplicity of integrated circuits is formed as individual dice on a semiconductor wafer. Such a multiplicity of integrated circuits may number in the tens to hundreds, or even thousands (such as in a 300 mm wafer) of individual dice which are generally repeated across the wafer in a two-dimensional array. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional with such a determination performed, generally, by probing each die individually. The probing of individual dice is performed using very costly probe equipment while the die is still in wafer form. Presently available probe equipment contacts each bonding pad on an individual die with a separate probe. A typical probe test requires that each die be probed in order to determine the correct and acceptable functionality of each die. However, due to the expensive nature of the probing test equipment, reliability testing (i.e., testing an individual circuit over time) is generally not performed.
It should be apparent that the purpose of wafer-level probing is to determine as early as possible in the manufacturing process the functional nature of each individual die. The earlier a defective die is detected, the fewer subsequent processing steps are performed on the defective die, which results in a reduction of costs associated with individual wafer processing. Upon the completion of functional probe testing, those defective dice are noted and subsequent manufacturing processes are not exerted.
Upon the identification of functional and nonfunctional dice, the dice are then separated or singulated by way of a dicing process. Following singulation, functional dice are packaged into integrated circuit packages or undergo further processing which allows the dice to be assembled as part of a higher-level assembly, which itself may be packaged. Once the dice have been packaged or prepared for packaging within a higher assembly, thorough electrical testing is performed to determine whether each packaged integrated circuit properly performs the functionality for which it was designed. Upon successful package testing, integrated circuits may be sold or integrated into higher assemblies.
An additional common manufacturing process includes subjecting the packaged integrated circuits to a form of reliability testing called burn-in. Burn-in testing involves testing an IC for an extended period of time at elevated operational temperatures. During the burn-in test, additional infant mortality failures manifest themselves and are further culled from the original multiplicity of manufactured dice. Burn-in testing may also utilize reduced temperature testing and may further include repetitive cycling of the packaged integrated circuit in an attempt to fatigue and fail frail ICs. Typical burn-in testing has utilized a concept of burning in packaged dice which have less fine-pitched inputs and outputs. Furthermore, the inputs and outputs of the packaged integrated circuit provide a more economical testing approach rather than the very fine-pitched probing mechanism used for individual die probing.
Conventional economical and high-volume approaches for burn-in testing of dice at a wafer level have required expensive and customized probing equipment. Therefore, there exists a need for a wafer-level testing methodology that does not require special processing or elaborate probe testing of individual integrated circuits at a wafer-level burn-in stage.